The FRV2000 MCU core has a Von Neumann memory architecture. Its pipeline is composed of 4 stages, as shown below:

•    Instruction Fetch (IF)
•    Instruction Decode (ID)
•    Instruction Execution (IE)
•    Register Write Back and Memory Access (MEM)

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However, unlike traditional pipelines, FRV2000 MCU’s pipeline stages are mapped to 2 x 2 layout, as illustrated above.

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In the 2 x 2 layout, each stage is active every other clock cycle. For the even cycle, only IF and IE stages are active, while for the odd cycle, only ID and MEM stages are active. In this way, the Instruction Fetch and Memory Access always happen on different clock cycles, thus to avoid the structural hazard caused by the single port memory.
 

Thanks to using single port memory to store both code and data, the FRV2000 soft MCU is quite portable and flexible across all FPGA platforms. Some FPGA platforms, like the Lattice iCE40 UltraPlus family, carry a large amount of SPRAM with very little EBR RAM. And those platforms will find themselves a good match with the PulseRain FRV2xxx when it comes to soft core MCU.

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