© 2019 by PulseRain Technology, LLC.

IP CORES

 

Engineers at PulseRain Technology are striving hard to develop IP (Intellectual Property) cores for ASIC / FPGA and electronic systems. The craftsmanship and reliability embodied in those pieces can greatly reduce TTM (Time to Market) and component cost without losing confidence in product quality.

FP51-1T MCU Core: A Mustang in FPGA

Putting MCU core into FPGA is becoming a universal practice these days. However, most MCU soft cores available today are tied to specific FPGA vendors. To break the status quo, PulseRain Technology has come up with the FP51-1T core (Named after the legendary P-51 Mustang Fighter-bomber.) for a more portable solution.

The FP51-1T is a high performance 8-bit MCU core, compatible with Intel 8051 ISA. With a crafty RISC implementation, this core can achieve single clock cycle execution for most instructions, while push the clock rate above 100MHz. (Silicon Proven on the low speed -8 grade device in Altera MAX 10 family). 

M10 High Speed Configuration for Intel MAX 10 FPGA
M10 High Speed Configuration
       -- Dual Boot Solution for Intel MAX 10 FPGA

Intel MAX 10 FPGA is widely adopted by various industries. However, the conventional solutions for its in-field upgrade all have their shares of shortcomings. To challenge the status quo and offer a general solution for in-field upgrade, PulseRain Technology has come up with its own answer: the M10 high-speed Configuration.

The M10 high-speed Configuration supports a throughput of 921600 bps, and can be used as a factory image. It also includes a Python based utility for user friendly interface.  And it is 100% open source for both RTL and software design.

ITU G723.1 (Annex A) Vocoder

 

The world's first FPGA / ASIC based multi-channel G723.1 codec, with industry's highest data throughput per clock cycle. It can support 4 channels simultaneously with a clock input of only 80MHZ.

 

The G723.1 vocoder includes a low rate (5.3 kbps) encoder and a dual rate (5.3 / 6.3 kbps) decoder. It also supports G723.1 Annex A for VAD (Voice Activity Detection) and CNG (Comfort Noise Generation).

 

This IP core has gone through rigorous verification process in both simulation and silicon. It has passed the full set of ITU test vectors with input of 4 PCM channels. It is also silicon proven on an Altera Cyclone III FPGA Dev Kit. Random packet loss has been emulated by hardware to verify the PLC (Packet Loss Concealment) capability of G723.1.

I2S Bus Transceiver

 

I2S is the bus protocol supported by most audio codec chips. PulseRain Technology's silicon proven I2S transceiver offers a seamless solution for audio codec / vocoder integration. Due to its smart elastic buffer design, CDC (Clock Domain Crossing) and flow control are turned into cinches during IP integration stage.

 

Together with our G723.1 vocoder, the I2S transceiver has been fully verified on an Altera Cyclone III FPGA Dev Kit to interface with Texas Instrument's TLV320AIC23B stereo audio codec.