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ITU G723.1 (Annex A) Vocoder

 

Introduction

 

The world's first FPGA / ASIC based multi-channel G723.1 codec, with industry's highest data throughput per clock cycle. It can support 4 channels simultaneously with a clock input of only 80MHZ.

The G723.1 vocoder includes a low rate (5.3 kbps) encoder and a dual rate (5.3 / 6.3 kbps) decoder. It also supports G723.1 Annex A for VAD (Voice Activity Detection) and CNG (Comfort Noise Generation).

This IP core has gone through rigorous verification process in both simulation and silicon. It has passed the full set of ITU test vectors with input of 4 PCM channels. It is also silicon proven on an Altera Cyclone III FPGA Dev Kit. Random packet loss is also emulated by hardware to verify the PLC (Packet Loss Concealment) of G723.1.

License

 

  • Licenses are available for single project, multi-project or unlimited project

 

  • IP formats available for purchase:

    • RTL source code in System Verilog

    • Obfuscated RTL source code

    • Netlist targeted to a specific FPGA technology

 

 

Please contact us to request a quote if you are interested.

 
Design Resources

 

  • Product Datasheet

 

 

 

 

 

 

 

 

  • Simulation Library / Test Vectors

Available upon request

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  • ICD (Interface Control Document)

Available upon request

 

  • Simulator Supported:

    • Modelsim

 

  • Commercial Evaluation Board

This IP has been verified on an Altera Cyclone III Development Kit, plus a daughter card from Terasic for audio codec. The FPGA used on board is Cyclone III EP3C120F780

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And it has also been tested on Terasic DE1-SOC board.

 

Anchor G723.1 Design Resources
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