M10 High Speed Configuration
Dual Boot Solution for Intel MAX 10 FPGA
Intel MAX 10 FPGA is widely adopted by various industries. However, the conventional solutions for its in-field upgrade all have their shares of shortcomings. To challenge the status quo and offer a general solution for in-field upgrade, PulseRain Technology has come up with its own approach: the M10 High-Speed Configuration.
As illustrated in the figure below, the M10 High Speed Configuration is composed of two parts: the boot image and the host program
The boot image is composed of the following sub-parts:
A PulseRain FP51-1T soft-core MCU
Dual port on-chip RAM to store code for the processor
Bootstrapper. Different from the conventional approaches, M10 High Speed Configuration does not take any user flash memory (UFM). Instead, it uses a bootstrapper to get code from the host PC, and initialize the dual port RAM with that code. Based on the code received from the host, the processor (FP51-1T) will carry out the job for In-field upgrade. Since the firmware code of the boot image is stored on host machine (Windows PC) instead of UFM, this solution is future proof!
The host program, on the other hand, runs on a Windows PC. In M10 High Speed Configuration, it is actually a python script (For those who don't have python installed, an exe file is also provided.). At its startup, the host program will communicate with the bootstrapper and download code to FP51-1T processor in the boot image. After that, it will bring out a GUI to let user write new images to CFM/UFM, as shown below. But no matter what, the CFM0 (the sector that stores the boot image) will remain unchanged.
This IP is offered. in dual licenses: an open source license (GPL v3) and a commercial license. Please contact us to request a quote if you are interested in obtaining the commercial license..
Technical Reference Manual
Commercial Evaluation Board
This IP has been verified on PulseRain M10 Platform. The FPGA used on board is MAX 10 10M08SAE144C8G